1. Field of the Invention
The invention relates in general to an input buffer, and more particularly to an input buffer which makes use of an enhancement mode NMOS (n-type metal oxide semiconductor) transistor and one or more CMOS (complementary metal oxide semiconductor) device to lower the gate-source voltage V.sub.GS (the relative voltage potential between the gate terminal and the source terminal) of the PMOS transistor of the CMOS device. Then, the degree to which the PMOS transistor is turned on can be lowered effectively, to satisfy the purpose of raising the stability of the lowest input voltage V.sub.IH representing a logic 1. The main input buffers which are currently in use include the NOR gate, the NAND gate, and the inverter. The input levels V.sub.IH /V.sub.IL (where V.sub.IL is the highest input voltage representing a logic 0) are, for example, 2.2V/0.8V, 3V/0V. In the manufacturing industry, the acceptable standard input level of V.sub.IH ranges from 2.2V to 3V, and the acceptable standard input level of V.sub.IL ranges from 0V to 0.8V. The PMOS transistor that is considered to be a pull-up transistor, cannot fully turn off the CMOS device, as the voltage V.sub.IH is in the range of about 2.2V to 3V. Therefore, the triple point of the input buffer shifts as the direct source voltage V.sub.CC shifts. In consequence, the voltage V.sub.IH characteristic varies greatly as the direct source voltage V.sub.CC varies.
2. Description of the Related Art
FIG. 1 shows a traditional NOR gate input buffer circuit. An enable signal EN is received at the gate terminals of a transistor P2 and a transistor N2. The enable signal EN controls the operation of the NOR gate. When asserted high, that is, when at a logic 1 level, the magnitude of the enable signal EN is about equal to the direct bias voltage potential (V.sub.CC or V.sub.SS, where V.sub.SS is a source voltage which is often coupled to the source terminal of the NMOS, transistor of an input buffer). Thus, the CMOS devices (transistors P2 and N2) which receive the enable signal EN, can be fully turned on or off.
An input signal I/P is provided from an external system. The usual input levels V.sub.IH /V.sub.IL of this TTL (transistor transistor logic) signal are 2.2V/0.8V. If the input level V.sub.IH is 2.2V and the direct source voltage V.sub.CC is 5V, the gate-source voltage V.sub.GS of the transistor P1 equals 2.2V-5V=-2.8V. Because the magnitude of threshold voltage of a PMOS transistor is about 0.6V.about.0.8V, the magnitude (2.8V) of the voltage V.sub.GS is, in general, higher than the threshold voltage of the PMOS transistor in general. Therefore, the transistor P1 turns on. The higher is the direct source voltage V.sub.CC, the higher is the degree to which the transistor P1 is turned on, that is, the greater is the current that flows through the transistor P1. If the enable signal EN is OV and the input signal I/P is 2.2V, then the output voltage V.sub.OUT is close to the level of the source voltage V.sub.SS. However, since the degree to which the transistor P1 is turned on is high, the output voltage V.sub.OUT rises. In consequence, the output voltage tolerance of the integrated circuit will be wider. In order to maintain the characteristics and functionality of input buffers in a normal state, raising the voltage level V.sub.IH is necessary.
FIG. 2 shows a circuit of a traditional input buffer of a NAND gate, and FIG. 3 shows a circuit of a traditional input buffer of an inverter. Both the traditional NAND gate and the traditional inverter have the same problems in maintaining the characteristics and functionality of input buffers.